To date, the semiconductor material most commonly used in semiconductor-on-insulator structures has been silicon. Such structures have been referred to in the literature as silicon-on-insulator structures and the abbreviation “SOI” has been applied to such structures. SOI technology is becoming increasingly important for high performance thin film transistors, solar cells, image sensors, and displays, such as active matrix displays. SOI structures may include a thin layer of substantially single-crystal silicon (generally 0.05-0.3 microns (50-300 nm)) in thickness but, in some cases, as thick as 20 microns (20000 nm) on an insulating material.
For ease of presentation, the following discussion will at times be in terms of SOI structures. The references to this particular type of SOI structure are made to facilitate the explanation of the invention and are not intended to, and should not be interpreted as, limiting the invention's scope in any way. The SOI abbreviation is used herein to refer to semiconductor-on-insulator structures in general, including, but not limited to, silicon-on-insulator structures. Similarly, the SiOG abbreviation is used to refer to semiconductor-on-glass structures in general, including, but not limited to, silicon-on-glass structures. The SiOG nomenclature is also intended to include semiconductor-on-glass-ceramic structures, including, but not limited to, silicon-on-glass-ceramic structures. The abbreviation SOI encompasses SiOG structures.
Various ways of obtaining SOI-structure wafers include (1) epitaxial growth of silicon (Si) on lattice-matched substrates; (2) bonding of a single-crystal silicon wafer to another silicon wafer on which an oxide layer of SiO2 has been grown, followed by polishing or etching of the top wafer down to, for example, a 0.05 to 0.3 micron (50-300 nm) layer of single-crystal silicon; and (3) ion-implantation methods, in which either hydrogen or oxygen ions are implanted, either to form a buried oxide layer in the silicon wafer topped by Si, in the case of oxygen ion implantation, or to separate (exfoliate) a thin Si layer from one silicon wafer for bonding to another Si wafer with an oxide layer, as in the case of hydrogen ion implantation.
The former two methods, epitaxial growth and wafer-wafer bonding, have not resulted in satisfactory structures in terms of cost and/or bond strength and durability. The latter method involving ion implantation has received some attention, and, in particular, hydrogen ion implantation has been considered advantageous because the implantation energies required are typically less than 50% of that of oxygen ion implants and the dosage required is two orders of magnitude lower.
U.S. Pat. No. 5,374,564 discloses a process to obtain a single-crystal silicon film on a substrate using a thermal process. A silicon wafer having a planar face is subject to the following steps: (i) implantation by bombardment of a face of the silicon wafer by means of ions creating a layer of gaseous micro-bubbles defining a lower region of the silicon wafer and an upper region constituting a thin silicon film; (ii) contacting the planar face of the silicon wafer with a rigid material layer (such as an insulating oxide material); and (iii) a third stage of heat treating the assembly of the silicon wafer and the insulating material at a temperature above that at which the ion bombardment was carried out. The third stage employs temperatures sufficient to bond the thin silicon film and the insulating material together, to create a pressure effect in the micro-bubbles, and to cause a separation between the thin silicon film and the remaining mass of the silicon wafer. (Due to the high temperature steps, this process is not compatible with lower-cost glass or glass-ceramic substrates.)
U.S. Patent Application Publication No. 2004/0229444 discloses a process that produces an SiOG structure. The steps include: (i) exposing a silicon wafer surface to hydrogen ion implantation to create a bonding surface; (ii) bringing the bonding surface of the wafer into contact with a glass substrate; (iii) applying pressure, temperature and voltage to the wafer and the glass substrate to facilitate bonding therebetween; and (iv) cooling the structure to facilitate separation of the glass substrate and a thin layer of silicon from the silicon wafer.
The resulting SOI structure just after exfoliation might exhibit excessive surface roughness (e.g., about 10 nm or greater), excessive silicon layer thickness (even though the layer is considered “thin”), unwanted hydrogen ions, and implantation damage to the silicon crystal layer (e.g., due to the formation of an amorphized silicon layer). Because one of the primary advantages of the SiOG material lies in the single-crystal nature of the film, this lattice damage must be healed or removed. Second, the hydrogen ions from the implant are not removed fully during the bonding process, and because the hydrogen atoms may be electrically active, they should be eliminated from the film to insure stable device operation. Lastly, the act of cleaving the silicon layer leaves a rough surface, which is known to cause poor transistor operation, so the surface roughness should be reduced to preferably less than 1 nm RA prior to device fabrication.
These issues may be treated separately. For example, a thick (500 nm) silicon film is transferred initially to the glass. The top 420 nm then may be removed by polishing to restore the surface finish and eliminate the top damaged region of silicon. The remaining silicon film then may be annealed in a furnace for up to 8 hours at 600° C. to diffuse out the residual hydrogen.
Some have suggested using chemical mechanical polishing (CMP) to further process the SOI structure after the thin silicon film has been exfoliated from the silicon material wafer. Disadvantageously, however, the CMP process does not remove material uniformly across the surface of the thin silicon film during polishing. Typical surface non-uniformities (standard deviation/mean removal thickness) are in the 3-5% range for semiconductor films. As more of the silicon film's thickness is removed, the variation in the film thickness correspondingly worsens.
The above shortcoming of the CMP process is especially a problem for some silicon-on-glass applications because, in some cases, as much as about 300-400 nm of material needs to be removed to obtain a desired silicon film thickness. For example, in thin film transistor (TFT) fabrication processes, a silicon film thickness in the 100 nm range or less may be desired. Additionally, a low surface roughness may also be desirable for a TFT structure.
Another problem with the CMP process is that it exhibits particularly poor results when rectangular SOI structures (e.g., those having sharp corners) are polished. Indeed, the aforementioned surface non-uniformities are amplified at the corners of the SOI structure compared with those at the center thereof. Still further, when large SOI structures are contemplated (e.g., for photovoltaic applications), the resulting rectangular SOI structures are too large for typical CMP equipment (which are usually designed for the 300 mm standard wafer size). Cost is also an important consideration for commercial applications of SOI structures. The CMP process, however, is costly both in terms of time and money. The cost problem may be significantly exacerbated if non-conventional CMP machines are required to accommodate large SOI structure sizes.
In addition, a furnace anneal (FA) may be used to remove any residual hydrogen. However, high temperature anneals are not compatible with lower-cost glass or glass-ceramic substrates. Lower temperature anneals (less than 700° C.) require long times to remove residual hydrogen, and are not efficient in repairing crystal damage caused by implantation. Furthermore, both CMP and furnace annealing increase the cost and lower the yield of manufacturing. Thus, it would be desired that hydrogen is at least partially removed before the anneal such that the anneal step can be reduced in duration.
Therefore, it would desirable to achieve results comparable to or better than those of CMP, possibly in combination with furnace annealing, but without either CMP and furnace annealing and their associated drawbacks.